Old 160pin GPU Pinout & Rendering Differences

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Old 160pin GPU Pinout & Rendering Differences

Post by nocash » July 5th, 2016, 9:05 am

Pinouts for the old PSX GPU (used on PU-7 and EARLY-PU-8 boards)...

IC203 - Sony CXD8514Q - Old 160pin GPU for use with Dual-ported VRAM
Unlike the later 208pin GPU's, the old 160pin GPU has less supply pins, and, it doesn't have a 24bit RGB output (nor any other video output at all), instead, it's used with a RGB D/A converter that reads the video data directly from Dual-ported VRAM (ie. special RAM chips with two data busses, one bus for GPU read/write access, and one for the RGB video output).

Code: Select all

  1                 VCC
  2                 GND
  3     cpu 205     /GPU   ---        via 22 ohm
  4     cpu 153     GPU.A2
  5     cpu 204     /GRD   ---        via 22 ohm
  6     cpu 203     /GWR   ---        via 22 ohm
  7     cpu 202     DACK2  ---
  8     cpu 76      /RES
  9                 VCC
  10                GND/shield---
  11    cpu 201     33MHzG ---        via 22 ohm
  12                VCC
  13                GND/shield---
  14    cpu 200     DREQ2  ---
  15    cpu 102     /IRQ1  ---
  16    cpu 159     HBLANK
  17    cpu 199     VBLANK ---
  18                ?
  19                ?
  20                VCC
  21                GND
  22    cpu 198     D31
  23    cpu 197     D30
  24    cpu 194     D29
  25    cpu 193     D28
  26    cpu 192     D27
  27    cpu 191     D26
  28                VCC
  29                GND
  30    cpu 190     D25
  31    cpu 189     D24
  32    cpu 188     D23
  33    cpu 187     D22
  34    cpu 186     D21
  35    cpu 185     D20
  36                VCC
  37                GND
  38    cpu 184     D19
  39    cpu 181     D18
  40    cpu 180     D17
 ----
  41    cpu 179     D16
  42    cpu 178     D15
  43                VCC
  44                GND
  45    cpu 177     D14
  46    cpu 176     D13
  47    cpu 175     D12
  48    cpu 174     D11
  49    cpu 173     D10
  50                GND
  51                VCC
  52    cpu 172     D9
  53    cpu 169     D8
  54    cpu 168     D7
  55    cpu 167     D6
  56    cpu 166     D5
  57    cpu 165     D4
  58    cpu 164     D3
  59                GND
  60                VCC
  61    cpu 163     D2
  62    cpu 162     D1
  63    cpu 161     D0
  64                GND
  65                VCC
  66    vram'a 27   A8'a
  67    vram'a 28   A7'a
  68    vram'a 29   A6'a
  69    vram'a 30   A5'a
  70                GND
  71    vram'a 31   A4'a
  72    vram'a 34   A3'a
  73    vram'a 35   A2'a
  74    vram'a 36   A1'a
  75    vram'a 37   A0'a
  76                GND
  77                VCC
  78    vram'a 60   D15'a
  79    vram'a 58   D14'a
  80    vram'a 55   D13'a
 ----
  81    vram'a 53   D12'a
  82    vram'a 50   D11'a
  83    vram'a 48   D10'a
  84    vram'a 45   D9'a
  85    vram'a 43   D8'a
  86                VCC
  87                GND
  88    vram'a 22   D7'a
  89    vram'a 20   D6'a
  90    vram'a 17   D5'a
  91    vram'a 15   D4'a
  92    vram'a 12   D3'a
  93    vram'a 10   D2'a
  94    vram'a 7    D1'a
  95    vram'a 5    D0'a
  96                VCC
  97    vrams  41   DSF                 ---
  98    vram'b 39   /CAS'b  (via 22 ohm)
  99    vram'a 39   /CAS'a  (via 22 ohm)
  100               VCC
  101               GND
  102   vram'b 2    DT/OE'b (via 22 ohm)
  103   vram'a 2    DT/OE'a (via 22 ohm)  ---
  104   vrams  26   /RAS    (via 100 ohm)
  105   vram'a 2x   /WE'a   (via 100 ohm) (both /LWE and /UWE)
  106   vram'b 2x   /WE'b   (via 100 ohm) (both /LWE and /UWE)
  107   vrams  63   /SE     (via 220 ohm) ---
  108   vrams  64   SC      (via 22 ohm)  ---
  109               VCC
  110               GND
  111   vram'b 60   D15'b
  112   vram'b 58   D14'b
  113   vram'b 55   D13'b
  114   vram'b 53   D12'b
  115   vram'b 50   D11'b
  116   vram'b 48   D10'b
  117   vram'b 45   D9'b
  118   vram'b 43   D8'b
  119               VCC
  120               GND
 ----
  121   vram'b 22   D7'b
  122   vram'b 20   D6'b
  123   vram'b 17   D5'b
  124   vram'b 15   D4'b
  125   vram'b 12   D3'b
  126   vram'b 10   D2'b
  127   vram'b 7    D1'b
  128   vram'b 5    D0'b
  129               VCC
  130               GND
  131   vram'b 27   A8'b
  132   vram'b 28   A7'b
  133   vram'b 29   A6'b
  134   vram'b 30   A5'b
  135   vram'b 31   A4'b
  136   vram'b 34   A3'b
  137   vram'b 35   A2'b
  138   vram'b 36   A1'b
  139   vram'b 37   A0'b
  140               VCC
  141               GND
  142               OSC 53.20MHz
  143               VCC
  144               GND
  145   cxa 6       ?       ---   via 220+2200 ohm "SCIN"
  146               VCC
  147               GND
  148   cpu 160     DOTCLK        via 22 ohm
  149               VCC
  150               GND
  151   rgb 18      rgb.18  ---
  152   rgb 20      rgb.20
  153   rgb 21      rgb.21
  154   rgb 19      rgb.19
  155   cxa 10      /SYNC   ---   via 2200 ohm "SYNCIN"
  156               ?             maybe /VSYNC as in newer GPU
  157               ?             maybe /HSYNC as in newer GPU
  158               VCC
  159               GND
  160   cpu 206     67MHzG        via 22 ohm
IC207 - SONY CXD2923AR - Digital VRAM to Analog RGB Converter (for old GPU)
This chip is used with the old 160pin GPU and two Dual-ported VRAM chips. The 2x16bit databus is capable of reading up to 32bits of VRAM data, and the chip does then extract the 15bit or 24bit RGB values from that data (depending on the GPU's current color depth).
The RGB outputs (pin 5,7,9) seem to be passed through transistors and capacitors... not sure how the capacitors could output constant voltage levels... unless the RGB signals are actually some kind of edge-triggering PWM pulses rather than real analog levels(?)

Code: Select all

  1                 ?
  2                 ?
  3                 Vxx
  4                 Vxx
  5                 RED         via Transistor and Capacitor?? to RIN
  6                 Vxx
  7                 GREEN       via Transistor and Capacitor?? to GIN
  8                 GND/shield
  9                 BLUE        via Transistor and Capacitor?? to BIN
  10                Vxx
  11                ?
  12                ?
  13                ?
  14                aGND ?
  15                aGND ?
  16                aGND ?
 ----
  17                GND
  18    gpu 151     gpu.151
  19    gpu 154     gpu.154
  20    gpu 152     gpu.152
  21    gpu 153     gpu.153
  22    gpu 148     DOTCLK  via 22 ohm
  23                GND
  24                Vxx
  25    vram'a 4    D0'a
  26    vram'a 6    D1'a
  27    vram'a 9    D2'a
  28    vram'a 11   D3'a
  29    vram'a 14   D4'a
  30    vram'a 16   D5'a
  31    vram'a 19   D6'a
  32    vram'a 21   D7'a
 ----
  33    vram'a 44   D8'a
  34    vram'a 46   D9'a
  35    vram'a 49   D10'a
  36    vram'a 51   D11'a
  37    vram'a 54   D12'a
  38    vram'a 56   D13'a
  39    vram'a 59   D14'a
  40                GND
  41    vram'a 61   D15'a
  42    vram'b 4    D0'b
  43    vram'b 6    D1'b
  44    vram'b 9    D2'b
  45    vram'b 11   D3'b
  46    vram'b 14   D4'b
  47    vram'b 16   D5'b
  48    vram'b 19   D6'b
 ----
  49    vram'b 21   D7'b
  50    vram'b 44   D8'b
  51    vram'b 46   D9'b
  52    vram'b 49   D10'b
  53    vram'b 51   D11'b
  54    vram'b 54   D12'b
  55                GND
  56                Vxx
  57    vram'b 56   D13'b
  58    vram'b 59   D14'b
  59    vram'b 61   D15'b
  60                GND
  61                GND
  62                GND
  63                ?     --- testpoint?
  64                GND
IC201 - 64pin NEC uPD482445LGW-A70-S or SEC KM4216Y256G-60 (VRAM 256Kx16)
IC202 - 64pin NEC uPD482445LGW-A70-S or SEC KM4216Y256G-60 (VRAM 256Kx16)
These are special Dual-ported VRAM chips (with two data busses), the D0-D15 pins are wired to the GPU (for read/write access), the Q0-Q15 pins are wired to the RGB D/A converter (for sequential video output). The 8bit /LWE and /UWE write signals are shortcut with each other and wired to the GPU's 16bit /WE write signal.

Code: Select all

  1 VCC
  2 /DT/OE
  3 GND
  4 Q0
  5 D0
  6 Q1
  7 D1
  8 VCC
  9  Q2
  10 D2
  11 Q3
  12 D3
  13 GND
  14 Q4
  15 D4
  16 Q5
  17 D5
  18 VCC
  19 Q6
  20 D6
  21 Q7
  22 D7
  23 GND
  24 /LWE
  25 /UWE
  26 /RAS
  27 A8
  28 A7
  29 A6
  30 A5
  31 A4
  32 VCC
 ----
  33 GND
  34 A3
  35 A2
  36 A1
  37 A0
  38 QSF
  39 /CAS
  40 NC
  41 DSF
  42 GND
  43 D8
  44 Q8
  45 D9
  46 Q9
  47 VCC
  48 D10
  49 Q10
  50 D11
  51 Q11
  52 GND
  53 D12
  54 Q12
  55 D13
  56 Q13
  57 VCC
  58 D14
  59 Q14
  60 D15
  61 Q15
  62 GND
  63 /SE
  64 SC
Later 208pin GPUs
Later 208pin GPUs are used with 'normal' DRAMs with single 32bit databus, the different video memory chips are looking as if there might be some timing differences between old and new GPUs.
The old 2x16bit VRAMs might be faster on accessing non-32bit-aligned memory addresses, and with the dual-ported vram they won't block GPU read/write access during RGB video output, so the old GPUs could be potentially faster - unless Sony optimized some other things in newer GPUs, then it might be vice versa.
Anyways, I have never did any GPU timing tests on the PSX hardware, neither for old GPUs nor new GPUs.

EDIT: See also viewtopic.php?f=70&t=1042 for decapped GPU pictures.
Last edited by nocash on August 4th, 2016, 8:57 am, edited 2 times in total.

org
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Re: Old 160pin GPU Pinout

Post by org » July 31st, 2016, 8:58 pm

I made additional research on connections between old GPU chips:

Image

(Open image in new tab for full scale)

(Based on older PU-8 motherboard scans: http://siliconpr0n.org/map/sony/pu-8_1-658-467-11/ )

Mentioned by Martin "142 OSC 53.20MHz" looks like plain GND to me.

Pad 145 is really Subcarrier OUT, passed to RGB Encoder IC501
Pad 155 is Colorbust SYNC, generated by GPU-160, also passed to RGB Encoder

I'll post more nice drawing later :)

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Re: Old 160pin GPU Pinout

Post by nocash » August 3rd, 2016, 11:15 pm

org wrote:(Based on older PU-8 motherboard scans: http://siliconpr0n.org/map/sony/pu-8_1-658-467-11/ )
Mentioned by Martin "142 OSC 53.20MHz" looks like plain GND to me.
Pad 145 is really Subcarrier OUT, passed to RGB Encoder IC501
Pad 155 is Colorbust SYNC, generated by GPU-160, also passed to RGB Encoder
Pin 142, no that isn't GND, it's going straight to the oscillator about 10mm next to the pin (via 150 ohm resistor)
Pin 145, ah, so "SC" means "subcarrier" aka the PAL/NTSC color clock... yes, just tested... the frequency changes between 3.5MHz and 4.3MHz when changing between NTSC and PAL mode (resulting in a gray picture when using the "wrong" mode, since the remaining components of the PCB won't expect that clock to change).
Pin 155, yeah, that's /SYNC... looks like /VSYNC ANEed with /HSYNC.
The siliconpr0n photos are also interesting because they're showing some chips with undumped CDROM firmwares, see viewtopic.php?f=70&t=557&start=100#p10138 do you know who owns those chips, and if there's a chance to get them dumped?

I've been doing some scope tests on the 160pin GPU, and figured out some more GPU pin details:

Code: Select all

  18    (test)      ?             always high ?
  19    (test)      ?             always high ?
  145   cxa 6       SCOUT         via 220+2200 ohm "SCIN" ;PAL/NTSC color clock
  151   rgb 18      memck1        (mem clock?)
  152   rgb 20      memck2        (mem clock?)
  153   rgb 21      BLANK         (high in HBLANK & VBLANK)
  154   rgb 19      /24BPP        (high=15bpp, low=24bpp)
  155   cxa 10      /SYNC   ---   via 2200 ohm "SYNCIN"
  156   (test)      /HSYNC        rate:65us=15KHz, low:3.5us
  157   (test)      /VSYNC        rate:20ms=50Hz, low:130us=TwoLines

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Re: Old 160pin GPU Pinout

Post by nocash » August 3rd, 2016, 11:50 pm

And, after hacking the xplorer protocol, I am now having some comfortable way to connect different PCBs to a PC (without needing hardmodding all PCBs), so it's time for some software tests...

My original GPU (and SPU) tests have been done on a PSone with PM-41 mainboard... doing the same tests on a LATE-PU-8 board (with 208pin GPU) are behaving exactly the same as on PM-41, so there seem to have been no changes during the later hardware revisions (apart from cost reduction or so).

However, doing the same tests on an EARLY-PU-8 board (with 160pin GPU) revealed a bunch of differences:

Code: Select all

early-pu-8 with old 160pin CXD8514Q gpu:
  gpustat.13 when interlace=off --> always 0 (instead always 1)
  gpustat.14 always 0 (reverseflag)
  gpustat.15 always 0 (texture_disable)
  gp1(10h:index7) = N/A (instead 00000002h version)
  gp1(10h:index8) = N/A (instead 00000000h zero)
  gp1(10h:index3..4) = only 19bit (instead 20bit)
  gp1(10h:index8..F) = mirrors of index0..7
  gp1(20h) = whatever ? (not tested yet, but it's used by many games when having detected an old gpu)
  gp0(E1h) = without bit12/13 (x/y-flip really unsupported on this gpu)
  gp0(03h) = N/A (doesn't take up fifo space) (instead unknown/unused command)
  dma-to-vram: doesn't work with blksiz>10h (new gpu works with blksiz=8C0h!)
  dma-to-vram: MAYBE also needs extra software-handshake to confirm DMA done?
early-pu-8 with old CXD2922BQ spu:
  some ADSR waveforms get stuck at fixed volume level
There are probably more differences on the GPU transfer/rendering timings, and the SPU's ADSR waveform issue needs more testing, too.
Unfortunately, I've only borrowed the EARLY-PU-8 board, I can probably keep it a few more days, but it would be nice to have an own EARLY-PU-8 board (or even older PU-7 board) in my collection so I could do more hardware tests in future - would be great if somebody could donate an old PSX console (or just an old PSX mainboard) for research purposes!

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Re: Old 160pin GPU Pinout

Post by nocash » August 4th, 2016, 8:56 am

Here are some more GPU differences: http://psx.amidog.se/doku.php?id=psx:gpu
Maybe the ignored LSBs for "Modulate" might explain the "color banding" effect mentioned in the viewtopic.php?f=47&t=1035 thread?

At the moment, I am trying to get my bios clone working on the old GPU.
One big mistake was that I've been doing the VRAM upload as 10h blocks of 8C0h words (should have been vice-versa, 8C0h blocks of 10h words, although it did somehow work on newer GPUs).
Another (still unsolved) problem is that I can't get the linked list upload working, the list is initialized with 800h entries via DMA6, then polygon's for the "PS" logo are added (if a CDROM with "PS" logo is inserted), and the mouse arrow is also added to the list (if a mouse is connected), and then the list is uploaded to GPU via DMA2.
I am doing the tests on a bare mainboard (without CDROM or Mouse), so the linked list should be completely empty... but somehow the console hangs when issuing the DMA2 linked list upload : - / I've added lots of delays & status waits, but that didn't help. One thing that did help was truncating DMA2 to send only the first 1..4 entries of the list, but the console hangs when sending 16 or more linked list entries.
Is that some known effect, DMA needing to be implemented somehow differently on old GPUs?
EDIT: Or actually, if my OT is really empty, then the DMA shouldn't ever even send anything from CPU to GPU. Gotta verify if my empty OT table is really intact. Either I've screwed up something... or the CPU/DMA hardware is also different as in later consoles...?
Last edited by nocash on August 5th, 2016, 9:57 am, edited 1 time in total.

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Re: Old 160pin GPU Pinout & Rendering Differences

Post by nocash » August 5th, 2016, 9:43 am

I've tested the "Modulate" and "Fill" issues mentioned on AmiDog's webpage. Both do occur on EARLY-PU-8 (160pin GPU), and both are fixed on LATE-PU-8 (206pin GPU) as well as on later boards like PM-41 (PSone).

See here for some more notes on the "Modulate" effect: viewtopic.php?f=47&t=1035#p10161

For the "Fill" glitch. The VramFill command does usually round-down the horizontal desination to a 16-pixel boundary. However, on the old GPU, if the destination is "(x AND 0Fh)=0Fh", then it's freaking out a bit: The coordinates for each 2nd pixel is rounded-down to start at 16-pixel boundary (as usually), but the coordinates for each other pixel are rounded-up to 16-pixel boundary.
That weird effect is possible because the old GPU used two VRAM chips with 16bit data busses, and with separate address busses (so each two pixels can be written to different addresses). The later GPUs are having only a single RAM chip with 32bit data bus, so it's more or impossible to implement the same glitch in that newer hardware design (in so far, it's possible that Sony fixed that glitch 'unintentionally', without ever noticing that the glitch did exist in old hardware at all).
In practice, the VramFill effect looks as so (with xloc=0..1Fh, width=20h, height=4):

Code: Select all

OLD GPU:
  0h              10h             20h             30h             40h
  |               |               |               |               |
  ################################                                     ;-
  ################################                                     ; xloc = 00h..0Eh
  ################################                                     ; (rounded down to 00h)
  ################################                                     ;/
   # # # # # # # ################## # # # # # # #                      ;-
   # # # # # # # ################## # # # # # # #                      ; xloc = 0Fh
   # # # # # # # ################## # # # # # # #                      ; (rounded up+down)
   # # # # # # # ################## # # # # # # #                      ;/
                  ################################                     ;-
                  ################################                     ; xloc = 10h..1Eh
                  ################################                     ; (rounded down to 10h)
                  ################################                     ;/
                   # # # # # # # ################## # # # # # # #      ;-
                   # # # # # # # ################## # # # # # # #      ; xloc = 1Fh
                   # # # # # # # ################## # # # # # # #      ; (rounded up+down)
                   # # # # # # # ################## # # # # # # #      ;/

NEW GPU:
  0h              10h             20h             30h             40h
  |               |               |               |               |
  ################################                                     ;-
  ################################                                     ; xloc = 00h..0Fh
  ################################                                     ; (rounded down to 00h)
  ################################                                     ;/
                  ################################                     ;-
                  ################################                     ; xloc = 10h..1Fh
                  ################################                     ; (rounded down to 10h)
                  ################################                     ;/
As for which coordinates are rounded up or down, that's (as shown above) opposite as one might expect: The should-be coordinates 0,2,4,6... are accidentally rounded-up to 10h,12h,14h,16h. Whilst coordinates 1,3,5,7... aren't rounded-up.

And, the other thing mentioned by AmiDog is the "Freeze" effect upon large VramToVram transfers... I haven't tested that one yet... Btw. what means "large" exactly? Large width and/or height?

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Re: Old 160pin GPU Pinout & Rendering Differences

Post by nocash » August 7th, 2016, 9:45 am

Got my OT stuff working, the main problem seems to have been that I didn't wait for the CpuToVram DMA to finish before starting the linked-list DMA (I did only wait for one of the GPUSTAT bits, but for the DMA busy bit). Not absolutely sure why my old code worked on 208pin GPU but not on 160pin GPU, maybe the DMA is faster on newer GPUs (and finished before starting the linked-list DMA), or the GPUSTAT bits have slightly different meanings on old GPU.

I've tried to reproduce AmiDog's "Freeze" effect upon large VramToVram transfers on a 208pin GPU (LATE-PU-8 board), but it didn't happen for me, even when trying really large xsiz+ysiz values (about the whole VRAM size, and even tried to EXCEED the VRAM size). More info would be nice! Some example with source/dest/size values that are known to freeze...
And some more info on how to send the command(s), with/without waiting for which GPUSTAT bits between the separate commands? Or sending commands as part of a linked list, so hardware should automatically (try to) use the correct timings?

Oh, and two things not really GPU related:

The SPU's ADSR difference occured just because I didn't initialize the Pitch & ADPCM waveform (so it must have immediately hit an ADPCM end+mute code, immediately forcing the ADSR level to zero). That problem occured on EARLY-PU-8 (any time after power supply was switched off for about a minute), but the problem didn't occur on LATE-PU-8 (and as far as I remember neither on PSone). So, the old SPU must somehow tend to 'initialize' the unitialized GPU registers differently (or the SPU RAM chips from different manufacturers tend to power-up with different values). Anyways, the old/new SPU's should work the same once when having initialized everything.

And, I've also noticed that the CPUs are a bit different: CXD8530BQ (EARLY-PU-8) and CXD8530CQ (LATE-PU-8) are both having PRID (cop0 register15) set to 00000001h, whilst CXD8606BQ (PM-41, PSone) as PRID=00000002h. Are there any known differences between old/new CPUs? Timings, pinouts, instruction set, registers, mdec, gte, dma, memory, whatever...?

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