Caetla 0.34+ CODE Format

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ly63
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Caetla 0.34+ CODE Format

Post by ly63 » June 11th, 2016, 2:45 am

Ordinary DOC is in japanese,I have translated it into English.
Japanese doc is here: http://www.ne.jp/asahi/lips/42st/codes.htm

-------------------------------------------------------------------------------
Note:

Byte = 8bit value
Halfword = 16bit value
word = 32bit value

All 16bit ram access code's address must be aligned to 2,
all 32bit ram access code's address must be aligned to 4.

-------------------------------------------------------------------------------


I.Ram write code

code 30

Format:
30XXXXXX 00DD
Explain:
Same as AR2/GS's 30 code.
write byte value 'DD' at address 80XXXXXX.

code 80

Format:
80XXXXXX DDDD
Explain:
Same as AR2/GS's 80 code.
write halfword value 'DDDD' at address 80XXXXXX.

code 90

Format:
90XXXXXX DDDDDDDD
Explain:
write word value 'DDDDDDDD' at address 80XXXXXX.

II.Copy memory code

code 70

Format:
70XXXXXX 80AAAAAA
Explain:
Copy byte value from address 80AAAAAA to 80XXXXXX.
Copy byte value from address 80XXXXXX to 80AAAAAA.
code 71

Format:
71XXXXXX 80AAAAAA
Explain:
Copy halfword value from address 80AAAAAA to 80XXXXXX.
Copy halfword value from address 80XXXXXX to 80AAAAAA.
code 72

Format:
72XXXXXX 80AAAAAA
Explain:
Copy word value from address 80AAAAAA to 80XXXXXX.
Copy word value from address 80XXXXXX to 80AAAAAA.

III.Bit manipulation code(set/clear bit)

code 50 (set bit)

Format:
50XXXXXX 00DD
Explain:
logic OR byte value at address 80XXXXXX with 'DD',then write the
result to 80XXXXXX.

code 51 (set bit)

Format:
51XXXXXX DDDD
Explain:
logic OR halfword value at address 80XXXXXX with 'DDDD',then write
the result to 80XXXXXX.

code 52 (set bit)

Format:
52XXXXXX DDDDDDDD
Explain:
logic OR word value at address 80XXXXXX with 'DDDDDDDD',then write
the result to 80XXXXXX.

code 58 (clear bit)

Format:
58XXXXXX 00DD
Explain:
First do logic NOT 'DD',the temp result is 'TT',then logic AND byte
value at address 80XXXXXX with 'TT',finally write the result to
80XXXXXX.

code 59 (clear bit)

Format:
59XXXXXX DDDD
Explain:
First do logic NOT 'DDDD',the temp result is 'TTTT',then logic AND
halfword value at address 80XXXXXX with 'TTTT',finally write the
result to 80XXXXXX.

code 5A (clear bit)

Format:
5AXXXXXX DDDDDDDD
Explain:
First do logic NOT 'DDDDDDDD',the temp result is 'TTTTTTTT',then lo
gic AND word value at address 80XXXXXX with 'TTTTTTTT',finally
write the result to 80XXXXXX.

Note on clear bit codes(58,59,5A)
If you want to clear some bits,the input mask DD should be 1,not 0.
For example:
Ram location 80038912 contains byte value 0x1F(00011111),and you want to clear
bit 0 and bit 3,the DD value should be 0x09(00001001),NOT 0xF6(11110110)!
The code would be:
58038912 0009
when execute,the value of target location would change to 0x16(00010110).

IV.Scrath pad ram write code

code 3F8

Format:
3F800XXX 00DD
Explain:
write byte value 'DD' at address 1F800XXX.
XXX range:000~3FF

code 8F8

Format:
8F800XXX DDDD
Explain:
write byte value 'DDDD' at address 1F800XXX.
XXX range:000~3FF

V.Repeat Write code

code B

Format:
BXXXYYYY 00ZZ
30AAAAAA 00DD
or
BXXXYYYY ZZZZ
80AAAAAA DDDD
or
BXXXYYYY ZZZZZZZZ
90AAAAAA DDDDDDDD
Explain:
This code type is similar to AR2/GS's 50 code.
Repeat XXX times,Counter is temp value i,i= 0 to XXX - 1,each time
writes value (D+i*Z) to address (80AAAAAA + Y * i).

VI.Conditional code

code D0

Format:
D0XXXXXX DDDD
any supported code
Explain:
The same as AR2/GS's D0 code.
If the halfword value at address 80XXXXXX equals DDDD, execute next
line of code(nested conditional code allowed).

code E0

Format:
E0XXXXXX DDDDCCCC
first line of code
...
...
number CCCC line of code
Explain:
If the halfword value at address 80XXXXXX equals DDDD, execute next
CCCC line of code(nested conditional code allowed).

VII.Bitwise Conditional code

code 60 (if bit set)

Format:
60XXXXXX 00DD
any supported code
Explain:
Logic AND byte value at address 80XXXXXX with 'DD',if the result is
none zero,execute next line of code,don't save the result.

code 61 (if bit set)

Format:
61XXXXXX DDDD
any supported code
Explain:
Logic AND halfword value at address 80XXXXXX with 'DDDD',if the
result is none zero,execute next line of code,don't save the
result.

code 62 (if bit set)

Format:
62XXXXXX DDDDDDDD
any supported code
Explain:
Logic AND word value at address 80XXXXXX with 'DDDDDDDD',if the
result is none zero,execute next line of code,don't save the
result.

code 68 (if bit cleared)

Format:
68XXXXXX 00DD
any supported code
Explain:
Logic AND byte value at address 80XXXXXX with 'DD',if the result is
zero,execute next line of code,don't save the result.

code 69 (if bit cleared)

Format:
69XXXXXX DDDD
any supported code
Explain:
Logic AND halfword value at address 80XXXXXX with 'DDDD',if the
result is zero,execute next line of code,don't save the result.

code 6A (if bit cleared)

Format:
6AXXXXXX DDDDDDDD
any supported code
Explain:
Logic AND word value at address 80XXXXXX with 'DDDDDDDD',if the
result is zero,execute next line of code,don't save the result.

The 6X codes of caetla should be more useful than D0 code when use as joker
command.
since these codes test bit rather than comparing whole value,the test result
would be true when desired button(s) pressed,no matter what status of other
buttons are.

VIII.Small mips machine code routine injection

code A

Format:
AXXXXXXX DDDDDDDD
DDDDDDDD DDDDDDDD
...
...
DDDDDDDD DDDDDDDD
Explain:
The originary japanese DOC does not provide useful infomation
about how to use this code type,only the format. :shrug

There is no end flag for this code type,so you can't input another
type of code after the AXXXXXXX code lines.

IX.Code mode switch

code FFFFFFFF

Format:
FFFFFFFF 000D
Explain:
caetla also support AR2/GS code types,some types are conflict
between each other,such as 50 code and E code.to enabling all kind
of codes,k-comm add a mode switch code.

D=0,all codes below this line are caetla codes,untill another
FFFFFFFF code.

D=1,all codes below this line are AR2/GS codes untill another
FFFFFFFF code.

d=0 is default,so you are not required to input FFFFFFFF code when
you are using pure caetla code.

for example,you can mix AR2/GS code and caetla code like below:

E00A01E8 01000003 (caetla's 16bit mutil line conditional code E0XXXXXX DDDDCCCC)
FFFFFFFF 0001 (mode switch to AR2/GS now!)
E00A02E9 0001 (AR2/GS's 8bit conditional code E00XXXXX 00DD)
80120DCC 270F
FFFFFFFF 0000 (mode switch to caetla again!)
90120DC0 05F5E0FF (caetla's 32bit write code 90XXXXXX DDDDDDDD)

X.AR2/GS codes supported by caetla

In AR2/GS mode,D1,D2,D3,E0,E1,E2,E3,50,10,11,20,21 codes should work.However
there is a bug in 0.34 version which prevents AR2/GS's 21 code from working
properly.The bug was fixed by version 0.35.
There were no new code types introduced by newer version of caetla.

EOF

ly63
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Re: Caetla 0.34+ CODE Format

Post by ly63 » June 15th, 2016, 2:40 pm

Found a error in the 7x code's explaination.
It has been corrected.

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sicklebrick
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Re: Caetla 0.34+ CODE Format

Post by sicklebrick » September 15th, 2016, 8:31 am

Oh, that's awesome, cheers for sharing :D

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