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Sony PlayStation 1 - Basic System Information

General information to do with the PlayStation 1 Hardware. Including modchips, pinouts, rare or obscure development equipment, etc.

Sony PlayStation 1 - Basic System Information

Postby Shadow » March 1st, 2012, 7:18 pm




PlayStation Specifications




Manufacturer: Sony Computer Entertainment.
Generation: Fifth Generation era.

PlayStation:
JP December 3, 1994,
NA September 9, 1995,
EU September 29, 1995,
AUS November 15, 1995.

PSone:
JP July 7, 2000,
NA September 19, 2000.

PlayStation / PSone Overview Information:
16.7 Million Colours
Resolution: 256x256 (min) - 640x480 (max)
Sprite/BG Drawing
Adjustable Frame Buffer
No Line Restriction
Unlimited CLUTs (Color Look-Up Tables)
4,000 8x8 Pixel Sprites with individual Scaling and Rotation
Simultaneous Backgrounds (Parallax Scrolling)
360,000 Polygons/sec
CPU: MIPS R3000A-Family R3051 @ 33.8688 MHz
Media: CD-ROM
Storage Capacity: Memory card
Discontinued: March 23, 2006
Units Sold: 102 million
Best-selling game: Gran Turismo - 10.85 Million Shipped (as of April 30, 2008)


Central Processing Unit:
(R3051) MIPS R3000A-Compatible 32-bit RISC Chip running at 33.8688 MHz
The chip is manufactured by LSI Logic Corp, with technology licensed from SGI
Operating Performance of 30 MIPS (Million Instructions Per Seccond)
Bus bandwidth 132 MB/s
4 KB Instruction Cache
1 KB non-associative SRAM Data Cache
2 MB of main RAM


Geometry Transformation Engine:
Resides inside the main CPU chip, giving it additional vector math instructions used for 3D graphics
Operating Performance of 66 MIPS
360,000 flat-shaded Polygons per second
180,000 Texture Mapped and Light-Sourced Polygons per second
Theoretical Polygon count in optimal conditions given by Sony
1 Million flat-shaded Polygons per second
500,000 Texture Mapped and Light-Sourced Polygons per second


Data Decompression Engine:
Also residing within the main CPU, it is responsible for decompressing images and video
Documented Device Mode is to read three RLE-encoded 16×16 macroblocks, run IDCT and assemble a single 16×16 RGB Macroblock
Output data may be transferred directly to the GPU via DMA
It is possible to overwrite IDCT matrix and some additional parameters, however the MDEC internal instruction set was never documented
Compatible with MJPEG and H.261 files
Operating Performance of 80 MIPS
Directly Connected to the CPU Bus


Graphics Processing Unit:
Handles 2D graphics processing separate from the main 3D engine on the CPU
Maximum of 16.7 Million Colors (24-bit Color Depth)
Resolutions from 256 × 224 to 640 × 480
Adjustable Frame Buffer
Unlimited Color lookup tables
Emulation of simultaneous backgrounds (for parallax scrolling)
Flat or Gouraud Shading and Texture Mapping
1 MB of VRAM


Sound Processing Unit:
Supports ADPCM sources with up to 24 channels
Sampling rate of up to 44.1 kHz
512 KB of Memory


CD-ROM Drive:
2x, with a maximum data throughput of 300 KB/s
XA Mode 2 Compliant
CD-DA (CD-Digital Audio)
32 KB buffer


BIOS:
Stored on 512 KB ROM
Access is prohibited by Sony


Memory Card:
128 KB of space in an EEPROM
Development Console: SCPH-5502 with 8MB RAM, MM3 Modchip, PAL 60 Colour Modification (for NTSC), DB-9 breakout headers for both RGB and Serial output and an Xplorer with CAETLA 0.34.

Development Computer: Windows 98, Pentium 3 [400MHz], 128MB SDRAM, DTL-H2000, DTL-H201A, 21" Sony Trinitron CRT, CD-ROM burner, 3.25" and 5.25" Floppy Diskette Drives and a ZIP 100 Diskette Drive.
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Shadow
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Joined: 31st Dec 2012
PlayStation Model: H2000/5502

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