While I busy with RLE algorythm description i want to tell you one error i found in your RLE decoding: rl_decode_block(blk,src,qt) for i=0 to 63, blk[i]=0, next i ;initially zerofill all entries (for skip) @@skip: n=[src], src=src+2, k=0 ;get first entry, init dest addr k=0 if n=FE00h then @@skip ;i...

RLE finished.

Just finish reversing RLE address counter. This is counter that sets up addres for store result of RLE decoding. It must be in zigzag order, but real result are: 00 01 08 10 09 02 03 0a 11 18 20 19 12 0b 04 05 0c 13 1a 21 28 30 29 22 1b 14 0d 06 07 0e 15 1c 23 2a 31 38 39 32 2b 24 1d 16 0f 17 1e 25 ...

RLE control progress: found 2 counters: 1) first is downcounter which takes number of empty RLE values (LEN in no$psx docs) and count them down to 0. it generates 3 signals: - current cunter value not zero - input LEN value not zero - counter finish counting (current value zero but start value was n...

Cool! Last sceme do clamping from -0x7FF to +0x7FF (result is signed 12bit) and one more strange operation. It round result to closest to zero even number (except -1). Whoops that's odd. And that might be why my software tests lead me to thinking that RLE output would be only 11bit wide, not 12bit....

Main RLE datapath is finished. Now all data went from beginning (unit04) to the end (unit05). Only different controls left until all RLE will be reversed. http://forum.emu-russia.net/download/file.php?mode=view&id=974 http://forum.emu-russia.net/download/file.php?mode=view&id=976 Last sceme ...

New sceme succesfully simulated. This is inverted sum again, but this time for 16 bits.
Inputs are new value and previous sum result right shifted by 2.

How this is used we see a bit later when I reverse control logic.

10 days and 200 cells later I almost finished new big calcilation block. It 3 times bigger than previous one and works with inverted values too. I still don't know calculation result (I think it will be sum as well). Next goal is to finish all inputs and outputs from this sceme and simulate it in lo...

Riddle of previouse sceme solved! That was usual inverted adder. It adds two number but both numbers and result are inverted. That's why creators of chip used custom logic instead of usual Full Adders (thay are used in IDCT multiplication). By the way I moved forward and traced a bit of control logi...

I spent whole week with RLE calculations I met. This sceme just add one 11 bit value to another 11 bit value and add one bit optionally. First value are shifted by 1. One additional bit is shifted two. Value 1 = A >> 1 Value 2 = B Carry = C >> 1 So less significant bit of value 2 just go to result w...

i finished basic data lined and start trace RLE calculation logic. It looks like a lot of logic elements merges in giant spiderweb. :geek: I don't understand the pattern yet. http://forum.emu-russia.net/download/file.php?mode=view&id=956 http://forum.emu-russia.net/download/file.php?mode=view&am...

Okay, then Unit 03 seems to be the FIFO for incoming data - which should be 32 x 32bit in size. Theoretically the FIFO output could be passed straight to the RLE decompression hardware - not quite sure why it's stored in Unit 04 before passing it to RLE decompression hardware. But well, maybe there...

Fine. What size is Unit 04? And are you sure that it's used only for RLE encoded data, or could it be a general purpose FIFO for incoming MDEC data? It might be also used for other incoming data (ie. from scaletable & quant table commands; though it's also possible that those commands are routi...

Sceme reordering is over. Now data inputs (unit 03) and RLE (units 04 and 05) are separated. All RLE related sceme are merged togather. Newest RLE progress are few outputs from unit 04 (row of NOTs and row of MUXes) and outputs from unit 05. Data from the top of the picture are went directly to IDCT...

Nor handles first 9 bit while and handles next 6 bit.

And all of them and last bit nanded. That gives us detection of value 0Ñ…FE00. So it seems to be RLE

Just finished output from unit04. Now I doubt that this is Scale Table Matrix because data is handled in very strange way. Outputs go to set of MUXes, ANDs, NORs, invertors and triggers. Data goes to first set of mux as pair of 8 bit. Triggers receive 10 bit, invertors get next 6 bit. Nor handles fi...

Akari, did you ever got that working? Feeding two factors to the circuit, and receiving some intact looking multiplication result from the outputs? I couldn't test it myself since logisim requires java. Would be very interesting to know if it works, and to know how many fractional bits it's strippi...

I created this topic to keep this community update with recent foundings in PSX CPU reversing. A lot of other news can be found on http://psxdev.ru/ and in this topic http://forum.emu-russia.net/viewtopic.php?f=13&t=4106 (in russian) It's already 3 and half month from the beginning of CPU revers...